Liquid Crystal Displays are now widely used in various display fields, such as family, public places, offices, and personal electronics-related products and the like. A liquid crystal display panel mainly comprises: a liquid crystal cell formed by an array substrate and a color filter substrate, a polarizing sheet and a backlight module or the like. There are a plurality of Thin Film Transistors (TFTs) arranged at intersections of gate lines and data lines, wherein the gate lines control the TFTs to be turned on or turned off, and when a TFT is turned on, a pixel electrode is charged or discharged via a data line; a voltage on the data line controls the magnitude of a voltage applied to liquid crystal molecules and in turn controls the deflection degree of the liquid crystal molecules, so that the light passing through the liquid crystal molecules can display different gray scales. A circuit for driving the gate lines is referred to as a gate driving circuit, and the gate driving circuit outputs scan signals to the gate lines sequentially, and the scan signals are usually generated by shift registers. As continuous development of requirements, sometimes it is necessary that the liquid crystal panel can perform a reverse display, and thus it is required that the shift register for gate driving has a bidirectional scanning function.
FIG. 1 shows a schematic structure diagram of a conventional gate driving circuit in the prior art, wherein the gate driving circuit comprises a plurality of stages of shift register units SR1, SR2, . . . , SRN connected in cascade for bidirectional scanning, wherein from SR2 to SRN−1, an output signal of each stage of shift register unit is supplied to a corresponding gate line, and is further input to a previous stage of shift register unit for serving as a Reset signal of the previous stage of shift register unit and to a next stage of shift register unit for serving as a Start signal of the next stage of shift register unit respectively. The gate driving circuit further comprises control signal lines V_F and V_R for controlling a forward scanning and a backward scanning, clock signal lines CLK1 and CLK2, and a low level signal line VSS (not shown) all connected to each stage of shift register unit, and further comprises a start pulse signal line VST (not shown) connected to a first stage of shift register unit SR1. Further, it is unnecessary for an output signal of a Nth stage of shift register unit SRN to be supplied to its next stage of shift register unit.
FIG. 2 shows a schematic structure diagram of a conventional bidirectional scanning shift register unit (i.e., an ith stage of shift register unit, i>1) in the prior art, and the structure mainly comprises a control module 20 and an output buffer module 30, wherein the control module 20 comprises inside a specific control circuit for the forward scanning and the backward scanning of the shift register unit, and the output buffer unit 30 mainly includes a pull-up TFT Tpu and a pull-down TFT Tpd, wherein gates of the pull-up TFT Tpu and the pull-down TFT Tpd are connected to a pull-up node PU and a pull-down node PD of the control module 20 respectively, and a drain of the TFT Tpu is connected to CLK2, and a source of the TFT Tpd is connected to VSS. Respective input terminals of the control module 20 are connected to a signal output terminal Vout(i−1) of the previous stage of shift register unit (i.e., the (i−1)th stage), CLK1, V_F and V_R, respectively. The operational process of the shift register unit (i.e., the ith stage of shift register unit) is as follows: when the control signal line V_F for forward scanning outputs a high level signal and the signal output terminal Vout(i−1) of the previous stage of shift register unit outputs a high level signal, the control module 20 charges the pull-up node PU so that the TFT Tpu is turned on, and discharges the pull-down node PD so that the TFT Tpd is turned off; when the CLK2 is at a high level, the CLK2 at the high level is output from the signal output terminal Vouti of the shift register unit (i.e., the ith stage of shift register unit) via the TFT Tpu; when the CLK2 is at a low level, the control module 20 discharges the pull-up node PU and charges the pull-down node PD so that the TFT Tpu is turned off and the TFT Tpd is turned on, and a signal at the low level VSS is output from the signal output terminal Vouti via the TFT Tpd.
The follow problem generally occurs in the specific design of the bidirectional scanning shift register unit: the gate of the pull-down TFT Tpd might be subjected to an over-bias so that the threshold voltage of the TFT Tpd varies, thus resulting in decrease of the stability of the shift register unit. Detail is as follows: as shown in FIG. 2, in order to output the signal at the low level VSS from the signal output terminal Vouti at the subsequent timings, it is required that the control module 20 charges the pull-down node PD to turn on the TFT pd when the CLK2 is in a high level state, so that the signal at the low level VSS is output from the signal output terminal Vouti via the TFT Tpd, and it is required that the potential of the pull-down node PD is maintained by the control module 20 when the CLK2 is in a low level state; therefore, the gate of the TFT Tpd is always in a high level state, the gate of the pull-down TFT Tpd might be subjected to an over-bias so that the threshold voltage of the TFT Tpd varies, which generates a great effect on the stability of the shift register unit. Besides the liquid crystal display panel, in the shift register unit and the gate driving circuit of other types of display panels adopting an array display substrate, the above problem also exists.